1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of reconstructing an alignment mark during shallow trench isolation (STI) process.
2. Description of the Related Art
Photolithography is a key process in manufacturing semiconductor devices, so it plays an important role on the fabrication of the semiconductor. In the general process of fabricating a device, completion of the device requires approximately 10-28 patterning and exposure steps. In order to transfer the pattern of the mask accurately onto the wafer, masks between different levels should be aligned prior to the exposure of the photoresist to avoid wafer failure, which is due to transfer error of the pattern.
In a conventional exposure process, an alignment mark corresponding to a mask is formed on the wafer, which alignment mark is provided to form the semiconductor devices. A step height produced by the alignment mark may provide a scattering site or diffraction edge during alignment. When the light source, such as a He--Ne laser of a wavelength of about 635 nm, is provided to irradiate the whole wafer, a diffraction pattern produced by the light projected on the alignment mark is reflected to a alignment sensor and a first order diffraction interferometer alignment system to achieve alignment. However, the step height of the alignment mark, less than 200 .ANG., for example, is not high enough to obtain an obvious diffraction. As a result, the alignment signal is too weak or the noise ratio is too strong, which makes the alignment signal indiscernible by the alignment sensor and misalignment thus occurs.
FIGS. 1A-1E are schematic, cross-sectional views illustrating fabrication of a semiconductor device according to prior process. Referring to FIG. 1A, a substrate 100 having an alignment mark 101 is provided and a pad oxide layer 102 is formed thereon. A silicon nitride layer 104 serving as a mask layer is formed on the pad oxide layer 102. Since the alignment mark 101 formed within the substrate 100 has at least a depression 150 and there is a step height 170 between the surface 103 of the substrate 100 and the alignment mark 150, a recess 105 is therefore formed within the silicon nitride layer 104 above the alignment mark 101.
Referring to FIG. 1B, the silicon nitride layer 104 is patterned by photolithographic technique to form a patterned silicon nitride layer 104a, and the pad oxide layer 102 and the substrate 100 are successively etched using the silicon nitride layer 104a as a hard mask. A trench 108 is formed within the substrate 100.
Referring to FIG. 1C, a liner oxide layer 110 is formed on the exposed substrate 100 within the trench 108. A silicon oxide layer 112 is then formed to fill the trench 108. Since the step height 170 between the alignment mark 101 and the surface 103 of the substrate 100 is smaller than the depth 180 of the trench, the recess 105 within the silicon nitride layer 104a above the alignment mark 101 can be filled with the silicon oxide layer 112 when the trench 108 is filled with the silicon oxide layer 112.
Referring to FIG. 1D, the silicon nitride layer 104a is used as a stop layer, the silicon oxide layer 112 on the silicon nitride layer 104a is removed by chemical-mechanical polishing (CMP) and a portion of the silicon oxide layer 112a is left in the trench 108. During CMP process, the silicon oxide layer 126 in the recess 105 also remains.
Referring to FIG. 1E, the silicon nitride layer 104a is removed to expose the pad oxide layer 102a, and the pad oxide layer 102a is then removed in a HF solution. The remaining silicon oxide layer 112a and the liner oxide layer 110 in the trench 108 serve as an isolation region 114.
The etching rate of the silicon oxide layer 112b is different from the etching rate of the silicon nitride layer 104a. During the process for etching the silicon nitride layer 104a, the silicon oxide layer 112b serves as a hard mask, which makes the silicon nitride layer 104a under the silicon oxide layer 112b difficult to remove. The silicon oxide layer 112b can be removed by the HF solution for etching the pad oxide layer 102a, but the etching time in the HF solution is too short to completely remove the desired thickness of the silicon oxide layer 112b. Therefore, the step height 170 in the depression 150 is not high enough due to the residual silicon oxide layer 112b and the silicon nitride layer 104a in the recess 105, and this causes misalignment.
In addition, the silicon oxide layer 112b can be removed by prolonging the etching time when the pad oxide layer 102a is removed by the HF solution. However, because the etching time for etching the silicon oxide layer 112b is hard to control, the silicon oxide layer 112a within the trench 108 is hence easily over-etched to cause damage to the isolation region 114.
Referring to FIG. 1F and FIG. 1G, in order to avoid the planarized silicon oxide layer 112b covering the alignment mark 101 during STI process, a photoresist layer 116 is further formed over the substrate 100. The silicon oxide layer 112b in the recess 105 is removed in a HF solution. The photoresist layer 116 is then stripped, and the silicon nitride layer 104a and the silicon oxide layer 102a are removed successively. The alignment mark 101 is reconstructed. However, it is necessary to provide an additional mask to reconstruct the alignment mark and as a result, the fabricating time for etching is increased and the cost is also raised.